The university is a public sector degree-awarding institute chartered by the. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.Ĭonfigurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.ĭesign for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.Ĭase Studies: emerging applications, applications in industrial designs, and design frameworks. Scope IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). The Sukkur IBA University is a higher education institute in Sukkur, Pakistan. specific cache optimisations, IET Computers and Digital Techniques, vol. Add open access links from to the list of external document links (if available). Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era. doi: 10.1049/iet-cdt.2012. Bibliographic content of IET Computers & Digital Techniques, Volume 6. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain.Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. The authors have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don-t Care Conditions. In the second technique, Hamming coding is complemented with bad line exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20). View IET bahri2017.pdf from ECE MISC at Virtual University of Tunisia. In the first technique, the authors implement a combined two-dimensional coding scheme using Hamming and Bose-Chaudhuri-Hocquenghem (BCH) codes to address fault rates greater than 5.
Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. Both proposed techniques are based on error correcting codes to tackle different fault rates. IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). The authors compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics.
The authors propose two fault-tolerance techniques for hybrid CMOS/nanoarchitecture implementing logic functions as look-up tables.